1. Field of the Invention
The present invention relates to a semiconductor device and a method of manufacturing the same and, more particularly, to a semiconductor device constituting an anode short type gate turn-off thyristor (to be referred to as a GTO hereinafter) and a method of manufacturing the same.
2. Description of the Related Art
In a conventional method of manufacturing a semiconductor device having a GTO structure, in order to connect an electrode to a GTO body, a brazing technique is used. An application of the technique will be described below with reference to FIG. 1. In this case, a silicon laminated structure consisting of a p-type P1 layer 1, an n-type N1 layer 2, a p-type P2 layer 3, and an n-type N2 layer 4 is formed first. The P1 layer is then brazed to an anode electrode plate 5 consisting of Mo or W by using an A1 layer 6 as a solder. Subsequently, gate and cathode electrodes 7 and 8 are respectively formed on the P2 and N2 layers. A peripheral portion of the resultant structure is beveled, and a silicone resin 9 is coated thereon. In a GTO of this structure, the P1 layer may be fused in the A1 layer 6 as a solder, so that the solder 6 and the N1 layer 2 may be brought into contact with each other at, e.g., a portion denoted by reference symbol A. A conventional technique for preventing this will be described below with reference to FIGS. 2 and 3.
FIG. 2 shows an anode short type GTO whose anode side is patterned. In this arrangement, an N1.sup.+ layer is partially diffused first, and a P1 layer is formed by diffusion. At this time, in order to prevent contact as described above, the N1.sup.+ and P1 layers are formed deep. However, since the N1.sup.+ layer is laterally diffused at the same time, a portion X.sub.N1.sup.+ is expanded, and a portion X.sub.P1 is reduced accordingly. As a result, an effective region of a current flow is reduced. In addition, fine control during patterning becomes difficult. Therefore, variations in GTO characteristics occur.
A GTO having an arrangement shown in FIG. 3 will be described below. In this arrangement, a P1 layer is diffused deep first, and an N1.sup.+ layer is diffused. This method is advantageous in that a portion X.sub.N1.sup.+ can be formed to be narrow. As described above, however, the P1 layer cannot be controlled due to lateral diffusion. In addition, a resistance component R (shown in FIG. 3) near the N1.sup.+ layer is increased, and the electrical characteristics are degraded.